تمرینات vhdl کتاب دکتر نوابی

عنوان : تمرینات vhdl کتاب دکتر نوابی
گروه درخواست : مدارهای منطقی و معماری کامپیوتر ( کار با زبان های verilog و vhdl)
شرح درخواست :

4.3. List all the transactions in the following description:
ARCHITECTURE sequential of timing_demo IS SIGNAL a, b, c: BIT : = '0'; BEGIN PROCESS BEGIN a <= '1'; b <= NOT a; C<= NOT b; WAIT; END PROCESS; END sequential;

4.5. Show the waveform on x:
ARCHITECTURE sequential OF saving all IS SIGNAL X rit := ''; BEGIN PROCESS BEGIN x <= TRANSPORT '0' AFTER 5 NS; x <= '0' AFTER 3 NS; x <= '1' AFTER 11 NS; WAIT; END PROCESS; END sequential;

4.6. For the architecture description shown below, show the list of all transactions on the signals. Include all initial transactions, final transactions, and those that are discarded. Each transaction should be specified as a parenthesized list of value and time (ut). Show the resulting waveforms on all the signals. The WAIT UNTIL statement suspends the process until the condition becomes true.
ARCHITECTURE examining OF problem IS
TYPE git IS ('2', '1', '0','X'); SIGNAL W: qit := '0'; SIGNAL X: qit; SIGNAL Y : qit := '2'; SIGNAL Z: qit := '1'; SIGNAL a, b: BIT; BEGIN
a <= '0', '1' AFTER 20 NS; b <= '0', '1' AFTER 40 NS; pl: PROCESS BEGIN W <= '1' AFTER 8 NS; W <= '1' AFTER 10 NS; WAIT UNTIL a = 'i'; W <= '0'; y <= TRANSPORT '1' AFTER 5 NS; WAIT UNTIL b = '1'; w <= '1' AFTER 10 NS; W <= '0' AFTER 13 NS; W <= 'Z' AFTER 08 NS;
y <= TRANSPORT '0' AFTER 12 NS; y <= TRANSPORTZ! AFTER 15 NS; WAIT; END PROCESS pl; 2 <= x; END examining;

4.13. Using a single signal assignment and using signal y as the source, generate signal x such that this new signal is a copy of y unless there are pulses on y that are greater than width w. Pulses longer than w are trimmed when they appear on x.
4.14. Given the following signal assignments, show all transactions placed on each signal. At each event, show transactions that are appended, overwritten, and expired. Show resulting waveforms on each signal.
ARCHITECTURE dataflow OF signals IS TYPE git IS ('0', '1'. Z' 'x'); SIGNAL a, b, c: qit := '0'; BEGIN
a <= '0', 'l' AFTER 20 NS, 'Z' AFTER 30 NS, '1' AFTER 40 NS, AFTER 50 NS; b <= TRANSPORT O', a AFTER 14 NS; c <= '1', a AFTER 10 NS, 'Z' AFTER 15 NS, b AFTER 20 NS; END dataflow;
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4.15. Given the following signal assignments, show all transactions placed on each signal. At each event, show transactions that are appended, overwritten, and expired. Show resulting waveforms on each signal.
ARCHITECTURE dataflow OF signals IS TYPE git IS ('0', '1', '2', 'X'); SIGNAL a, b, c: git := '0'; BEGIN a <= NOT a AFTER 10 NS WHEN NOW <= 30 NS; b <= '2', a AFTER 25 NS, TO AFTER 35
<= '1', a AFTER 5 NS, b AFTER 20 NS; END dataflow;
de trans

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